There are kinds of voltage regulators for different needs. For example, some voltage regulators are provided for producing the drop-out voltage, which is the voltage difference between the output voltage and the input voltage in a normal operation. In circuitry applications, if the applied voltage is higher than the minimum operating voltage, it will result in the waste of power. Some other voltage regulators are provided as low drop-out voltage regulators (LDO) to limit the drop-out voltage, so as to make the output voltage close to the input voltage. LDO is mainly adopted in devices having low voltage sources, such as batteries. Some examples for this kind of devices are mobile phones, digital cameras, PDAs, laptops, GPS, etc.
As shown in FIG. 1A, a conventional LDO 100 includes a regulating circuit 102, a voltage divider 104 (also known as a potential divider), and an error amplifier 106. The regulating circuit 102 receives Vin from an external circuit (not shown) and generates Vout. The voltage divider 104 receives Vout from the regulating circuit 102 and passes it to the error amplifier 106. Then the error amplifier 106 feeds the Vout back to the regulating circuit 102.
FIG. 1B shows more details of the LDO 100. The regulating circuit 102 is implemented as a p-type metal-oxide-semiconductor field effect transistor (PMOS), and the voltage divider 104 adopts resistors 110 and 112 connected in series. LDO 100 receives input voltage Vin at its input and generates regulated output voltage Vout at its output. The gate of PMOS 102 receives the output voltage from the error amplifier 106. The positive input of the error amplifier 106 receives a reference voltage Vref, and the negative input receives feedback voltage from the voltage divider 104. The voltage divider 104 decreases the output voltage Vout to a fraction which is associated with the resistance of resistors 110 and 112, and feeds it into the negative input of the error amplifier 106 to compare with the reference voltage Vref. Then the error amplifier 106 generates regulating voltage to compensate or counteract the less stable output voltage of LDO 100.
If the output voltage Vout exceeds a predetermined level, the voltage at the negative input of the error amplifier 106 will go up. Thus the voltage difference between the positive and negative inputs will increase and bring up the gate voltage of PMOS 102. The increasing gate voltage of PMOS 102 will change the source-drain current and regulate the output voltage Vout and thus keep it stable.
However, the error amplifier 106 adopted in the conventional LDO 100 will consume a lot of power. And in some situations the use of voltage divider 104 may make the output voltage Vout unstable.
Therefore it is desired to have a novel display system adopting a simple, easy, and power saving way and less circuit elements to achieve the lower drop-out voltage.